Memory updating



Nov. 19, 1963 D. E. KEEFER MEMORY UPDATING Filed OG- 7. 1960 2 Sheets-Sheet 1 I0 C COUNT PULSE INVENTOR DAVID E. KEEFER f 'ATTORNEYS Nov. 19, 1963 MEMORY UPDATING Filed Oct. 7. 1960 2 sheets sheet 2 ADDEND ET-To DRIVER s'="T'ro.0 DRIVER FFO I j l:

INVENTOR DAVID E KEEFER Mm] *M ATTORNEYS United States Patent O 3,111,559 MEMRY UPDATENG David ld. Kaefer, Houston, Aex., assigner to Sperry Rand Corporation, New Yon-lr, NX., a corporation o Delawere lied (Bet. 7, 1969, Ser. No. 61,276

31 Claims. fll. 23S-175) This invention relates to la memory with updating provisions, and in particular to the updating of Ia binary number in at least one register by decimal l, or by -a binary addend.

The main object or" this invention is to provide a single register, or a plurality of registers, for example as in a computer memory device, with the capability of Ibeing updated directly, i.e., without iirst having to read the Iword out of the register in question.

The invention is illustrated in two different embodiments one of which may be referred to as ya counting memory, and the other or 4which may be referred to as -an adding memory. in the counting memort the binary -word in a .given refister may be directly lincremented by a decimal count of l while it is still in that register. in the adding memory, the binary word of a given register may be directly added to in laccordance with a binary addend, or ymay be updated by demical 1 in the same manner as the counting memory if no end-around carry is employed. Therefore, this invention has the advantage of eliminating all external registers or counters previously required for `addition or counting, except of course the addend register. ln addition, the speed or the counting operation lin the one embodiment, and of the summing operation in the other embodiment, is greatly increased over prior `art methods.

Therefore, a further object of this invention is the provision of memory updating apparatus which Aallows updating of a binary Word without removal thereorc from its original register.

Another object of the invention in conjunction `with the preceding object is to greatly increase the speed of the updating operation over that Iwhich was heretofore possible.

Still other objects of this invention will become lapparent to those of ordinary skill in the `art by reference to the following detailed description of the exemplary embodiments of the apparatus and the appended claims. The various features of the exemplary embodiments according to the invention may be best understood with reference to the accompanying drawings, wherein:

FIGURE 1 -is `a schematic illustra-tion of a counting memory, and

FiGURE 2 is a schematic illustration or" an adding memory.

FGURE 1 illustrates la counting memory, i.e., a memory with updating provisions. ln particular, the counting memory is of the type in winch a binary word stored in a register 'nay be increased by a value oi decimal l, upon the application of ya count pulse to input line it?.

Each binary word is stored in a register which comprises a plurality of bistable stages each or" which is switchable between first and second stable states. For example, what migh be referred to las Word No. l is stored in the register comprising bistable stages d2, le, le, `and Ztl, while binmy words numbers 2, 3, 4 yand 5 are stored in the `different groups of bistable stages respectively comprising stage groups 22-353, 324th and .d2-6l?. Preferably, each oi the stages in the memo-ry array -is a bistable magnetic element, `and more preferably each such element is a ferromagnetic film such as of the type producible in accordance lwith the Rubens Patent No. 2,900,282. In ysuch cases, the iilms will have uniaxial anisotropy with a single easy axis of magnetization :and

tlllii Patented Nov. 19, 1963 Ia lsingle hard axis of magnetization transverse to the easy axis, and they are preferably limited in thickness to a single domain. Such films are generally referred to as being thin Ferromagnetic as used in this `application is intended to include reference to any magnetic element which exhibits `ferro-magrietism and has a net amount of remanence, and so includes ferromagnetic materials (eg, the ferrites), but not antiferromagnetic materials which exhibit no net remanence.

Any suitable `magnetic element which is bistable and has a remanent magnetization `axis whereby the Itwo diffferent stable states are respectively represented by magnetization in opposite directions `along that axis, may be employed as Ithe bistable element for each stage of each Word register. When the memory includes more than one such register, it is desirable to be able to select any one register as opposed to all of the other registers. This may be accomplished by priming each bistable stage in iany one register. When the registers ycontain magnetic elements, such priming may be effected by magnetically biasing each 4such element in a register. When so primed or biased, any stage `in a so selected register may be switched from its instant stable state to the other upon receipt of -a further signal. To erect biasing of each magnetic element in any register of FIGURE 1, there Iare provided a plurality of switches, one for each word register, such as flip-hops 62, 64, 66, 63 and 7d. When any one of these dip-hops is set by means not shown, to one of its states, an output signal is applied to the respective bias generator B 'to cause a signal on the associated one oi lines 7E-Sil. This signal effects `a field which is caused to be transverse of the remanent or easy mag -etization axis or each of the magnetic elements associated with it, by the orientation of the field in the 'area of coupling to each element Aeifected by input `lines 72-8ii. F or magnetic lrns especially of the uniaxial anisotropy type, the transverse held applied thereto by one of lines '-t is along the hard or diicut nlm' axis, which is substantially orthogonal to the easy axis thereof. Also, with such films, the presence of -a transverse field allows a eld applied `along the easy axis to elect switching of the lm, but only if the transverse eld is present. That is, the field yapplied along the easy axis, generally referred to as the longitudinal eld, alone Inlay be made insufficient to switch a iilm except in the presence of a transverse held. However, yas above indicated, if there is only one binary word register which is to be updated, .the application of a transverse eld to each magnetic element in the register is unnecessary, since there then needs to be no selection of one register yas opposed to others. In such a oase, the transverse field applying means may be dispensed with 4as llong as the longitudinal held is made large enough to itself switch the magnetic element. Without the aid of a transverse eld, however, switching of the magnetic elements will be slower, much slower if the elements are films Vwhose magnetization vectors are rotated in accordance with the teachings in the Rubens et al. application, Serial No. 626,945, iiled Becember 7, 1956, now Patent No. 3,030,612.

The count pulse arriving on line 1t) is applied in parallel to a delay 82 and a driver 84, which may have ampliiication properties as desired. Whenever driver 84 applies a signal to its output line 86, which is an input line for the order of elements, that signal functions to set any one of the lower order magnetic elements 12, 22, 32, 42, 52 rwhen it is biased by a transverse iield, to its 1 state, considering that state as corresponding to Ithe binary 1 of a lower order digit of a stored word. If the biased lower order element is already in its 1 state, no change in state is eiected by the input signal on line 86. Conversely, if the biased lower order element is in its 0 state, the input signal via line S6 causes that element to change to its l state. Consequently, line S6 may therefore be thought of as a set-to-l input to the lowest element order whether a signal on line 86 actually changes the biased elements state from to 1 or just does not change it from 1, with driver S4 correspondingly being a set-to-l driver. These two different situations are represented by the horizontally disposed numbers within elements 22 and 32 above their respective transverse ield applying lines 74, 76, with the number on the left of line 88 (fourth quadrant, so to speak) representing the initial state of Vthe element as well as the initial binary value of the lower order digit of the respective stored Word.

Since element 32 changed state under the assumptions above given, an appreciable signal is induced in output line 8S which couples all of the lower order elements. Consequently, that signal on line $3 via sense amplifier 90 when applied to the inhibit input 92 of an And-Not circuit or inhibit gate 94, is suficient to prevent passage of the delayed count pulse to the output 96 of gate 94. However, if the biased element is element 22 which is initially in its 1 state, the input signal on line 86 does not cause a change of state of that element. Therefore, no appreciable signal is applied via output line $8 to amplifier 90, and the delayed count pulse as Anded with the inverted output of amplifier 9G is passed to the inhibit gate output 96. This output signal is applied in parallel to delay 98 and a set-to-l driver 100 for the second column or order of magnetic elements. The resulting signal from driver 100 is coupled by line 111-2 as an input signal to each of the elements 14, 24, 34, 44, 54 (the second order elements) to aiect the biased one of those elements in the same manner as previously described for an input signal on line 36 relative to the lowest order of elements. Line 1612 is also connected to line 104, serially as shown though the two lines could be in parallel. Line 104 couples each of the magnetic elements in the lower order in a direction opposite to the coupling thereof by line 86. Consequently, any signal passed by gate 94 is effective via line 1114 to switch any biased element in :the lower order to its O state. This is indicated for magnetic element 22 by the number therewithin below line 74 (second quadrant). Line 1114 may consequently be thought of as a set-to-O input.

In retrospect, then, it will be apparent that if element 22 were the Vselectively biased lower order element, it would not be switched by an input signal on line 86 because it was initially in a 1 state and the polarity of that signal and resultant field is such as to cause that element to remain in its 1 state. As a consequence of such no switching a signal would result on line 164 causing element 22 to switch to (l. On the other hand, if element 32 were the selectively biased lower` order element and its initial state were 0 as above assumed, it would be switched by a set-to-1 signal on line 86 causing an output signal to gate 94 which inhibits passage of the delayed count pulse and consequently prevents any set-to-(l signal on line 104. In other words, due mainly to the And-Not function of inhibit gate 94, a biased element of -the lowest order gets switched from its second state (1) to its first State (0) by the delayed count pulse via line 1114 only if that element was not initially switched by the count pulse via line 86 from its first state (0) to its second state (1).

The delay factor attributable to delay 82 depends upon the circuit constants, and is such as to provide an output to gate 94- at a time coincident with any output from amplifier 96 caused by a signal on line 36. In general, the delay of the count pulse through delay S2 may be said to be substantially equal to the sum of the delays offered by driver 84, sense amplifier 90, and lines 36 and 88. The time delay associated with delay 98, and all the other delays Vin FIGURE 1, as well as in FIGURE 2, may be similarly calculated.

The count pulse on line 1f), when propagated through gate 94, operates via driver 10ft and line 102 to set the biased one of the second order magnetic elements 14, 24, 34, dat, 54 to its 1 state if not already therein, in the same manner as previously described that the count pulse via driver 84 operates on the biased one of the lower order elements. if the biased element in the second order changes from 0 to 1 due to a signal on line 1112, then an output signal is induced on output line 1% causing the count pulse as again delayed, this time by delay 98, to be inhibited from passing through inhibit gate 1198. The output signal on line 166 may be amplified by an amplifier 11% is desired. However, if the biased element in the second order is already at 1 when a pulse is applied via line 162 and consequently does not change state, gate 103 passes the delayed count pulse to the third order delay 112 in parallel -with the third order set-to-l driver 114. The output of that driver is coupled by line 116 to a set-to-l input of each of the third order bistable elements 16, 26, 36, 46, 56, and by linel 118 to the set-to- 0 input of `the second order of the elements. Consequently, operation of the elements in the second order is the same as that described for the first order elements. Further, since each of the other orders of elements similarly has a set-to-l driver and input and a set-to-O input as well as an associated delay and inhibit gate with the output of any one inhibit gate being coupled to the input of the next higher order delay in parallel with the input to the next higher order set-to-l driver D assuming there is such a next higher order, the operation of all the orders is the same as that above described for the first and second orders.

As an example of the overall operation of the counter, assume the binary number stored in the register comprising elements 22-3@ is 10011 the equivalent of decimal 19. With such a binary number stored in the register, element 30 is in its 1 state as indicated in the drawing in the fourth quadrant of that element, elements 26 and 2S are in their 0 states, and elements 22 and 24 are in their l states. Further, assume that the word in this register is the one to be updated by decimal 1. To select this register to the exclusion of others, each bistable stage must be primed. Therefore, flip-flop d4 is set to cause via its biased generator B a signal on line 7d which eects a transverse field for each of the bistable elements in the register. This biases each of those elements tending to rotate the magnetization thereof away from its easy axis.

At the same time, or subsequently while the transverse fields still exist, a count pulse is applied to line 1t). The consequent output of driver 84 as it appears on line 86 has no effect on the biased magnetic element 22 since that eiement is already in its 1 state. Hence, no appreciable signal is induced in sense line 88, and the first order inhibit gate 94 is consequently capable of passing the delayed count pulse. The output of gate 94 may be considered a carry pulse which when applied via driver 19@ to each of the second order magnetic elements not only assures that element 24 is at 1, but also causes, via its return path 1134, element 22 to change to 0. Since element 24 was already in its 1 state, no switching occurred due to the pulse on line 162. Therefore, appreciable output results on line 106, and gate 1413 is not inhibited but passes the delayed carry pulse to the third order units.

The output or driver 114 is applied by line 116 to all of the elements in the third order and causes the biasedl element 26 to change lfrom 0 to 1, and additionally via. line 118 causes element 24 to change from 1 to 0. Thechange of state of element 26 causes an output signal on. line 121B which through amplifier 122 inhibits the passageof a pulse from delay 112 through inhibit gate 124. Consequently, neither delay 126 nor driver 128 receives any input signal. This means that there is no input pulse on the set-to-1 input line 13@ for the fourth order of elements, and no input pulse on the set-to-O input line 131 for the third order of elements. Elements 26 and 2S therefore do not change from their respective 1 to 0 states. Since element 2S does not switch, no pulse: on output line 132- 5, results. Gate 13d is therefore not inhibited but since gate 124 provided no output to delay E26, there is no output pulse from gate 134; hence there is no pulse gated through driver 135 and over line 138 to the set-to-(l input line 139 for the fourth order of elements. Element 23 consequently rernains at O. For the same reasons, the state of eiernent El@ is not changed. That is, with no input signal on line 13S, no output signal results on line 1.4i) to inhibit gate 142, but with no pulse into delay 144i no pulse passes gate 142 to dri er 10.16. Therefore, there is no pulse via line 148 to the set-to-G input of the fifth order of elements, so element 3i? remains at l. As shown in the second quadrant in each of the word No. 2 stages, the resulting word is the binary number lOlOO, which is equivalent to the decimal number 20. In other Words, the number in the register has been incremented by decimal l.

The second embodiment of a memory with updating provisions is shown in FIGURE 2 which particularly relates to an adding memory. This memory, as well as the one in FIGURE l, is of the word organized type. Only two registers, each with three `bistable stages, is illustrated, but of course either of these numbers may be increased or decreased, the saine as `for the el lbodimtent of FIGURE l. The first register comprises bistable stages 150, 152 and 154, while the second includes bistable stages 155, 15S and 169. Again, each oi these stages may be as described for the respective stages in the EEGURE 1v array, and the description will proceed as though they are each a mag netic element. For purposes of selecting one or the other of the registers, dip-flop type switches 152 and 164 may be employed so as to eect through their respective bias generators B, a signal on one or the other of lines 166, 163. Such a signal effects a field which is transverse to the remanent or easy aids magnetization of the magnetic elements. When all the elements in any one register are iased, that register is selected for updating in accordance with the contents of the addend register 170. Each binary stage in the addend register is respectively coupled at its output to an Or circuit. For example, the lowest order stage of the register is coupled to Or circuit i72, the second stage to Or circuit 174, and the third or highest order stage of the illustrated register is coupled to Or circuit 176.

When a pulse is applied to Or circuit l72, that pulse is conveyed in parallel to delay 17S and a driver 184i, the output of which is coupled to line 132. This line links each element in the lowest order or" elements, and consequently any signal on that line, due to its polarity, tends to svvitch any biased element to the state associated with the polarity of that signal. In this case, the driver 18() is a set-to-Q driver so that it element ll is presumed to be in its l state initially, then it is switched to its 0 state if line 166 is concurrently activated. However, ir" as shown for element i513, the initial state oi the biased element is 0, then there is no change of state thereof due to a signal on line 182.

With no change of the biased element in response to a signal on line 1F52, no appreciable output signal is induced on output line 32d. Consequently, there is then no inhibiting by a signal to the inhibit input .lee via amplier 18d, and inhibit gate passes the delayed pulse to a set-to-l ldriver 192, the output or" which is also coupled to input line 1%2. output signal fro-rn driver i925 consequently changes the biased but unswitched element to its l state. Un the other hand, if a biased element in the lowest order is uwitched due to a signal `from driver li), the inhibit gate it prevents any passage of the delayed signal and consequently there is no output from driver 192, maintaining the previously switched element in the state to which it was switched by the signal from driver 18o. ln other words, due mainly to the And-Not function of inhibit gate 19t?, a biased element of the lowest order gets switched from its second stat-e (O) to its first state (l) by the delayed pulse via driver 192 only if that element was not initially switched from its first 6. state (i) to its second state (0) by the pulse as applied via driver 18?.

The output of `delay 17S is also coupled to 'gate 19d. This gate is of the non-inhibit type and receives at its second input the sensed output signals via amplifier 18S. When there is -coincidence of the inputs to gate 194, those inputs are effectively Anded to provide an output `from gate 19d on line 1%. This applies an input to Or circuit 174, which otherwise may receive an input from the second stage of the addend register 17h.

The second and third orders of elements have their respectively associated drivers, gates, and delays operated similarly to the way described for those associated with the iirst order.

To exemplify the operation completely, the binary number `(il l, decimal 3, may be assumed to be stored in the selected register, for example in magnetic elements 15d-154, While the same binary number is stored in the addend register 17h. Under these conditions, a pulse, 1indicative of a binary 1, appears on the two lower output lines from the addend register respectively to Or circuits 172, 17d, Consequently, magnetic element 15@ will be switched from l to 0, causing a carry signal to be propagated rom gate 1% t0 Or circuit 174i. Previously, and at the same time as element l5@ was so switched, element 152 was also switched but by the output from the second stage of the addend register. That is, the pulse from that stage as applied through driver 1% switched element 152 from l to G, and effected an output signal on sense line Gate was thereby inhibited but gate 21M enabled to pass the pulse from the addend register via delay 265, as a carry pulse to 0r circuit 176. At this same time, the previously generated carry pulse on line 1% as presented to element 152 via set-tolti driver 193, has no effect on element since it is already in its G state. However, this lack of switching provides no inhibit pulse to gate 292, and the `delayed carry pulse is applied therethrough to driver 2% which resets element 152 to 1.

rl`he initial switching of element 152 from l to 0 caused an output from the And gate Ztid, and this output is applied `via 0r circuit No to delay 2l@ and the set-to-G ydriver 212. Since element 154 was initially in its 0 state, no switching thereof is thereby effected. However, this lack or" switching allows the carry pulse which arrives via delay 2l@ to pass inhibit gate 21dand energize the set-to-l ydriver 1215, causing element 154 to chan-ge to its l state. This change of state of element iSd causes a signal to be induced on output line 213, but this induced signal is of the wrong polarity to be Anded in gate 22@ with the output of delay 21h. Consequently, there is no endaround carry pulse via line 222 for energizing 0r circuit 172.

From the above description, it will be apparent that elements :152 and 154i. have been changed to their l states,

while element 159 has been changed to its 0 state, Vgiving a resulting binary number of which is equal to decimal 6. Addition of the binary number in the addend register 17S* and the particular augend register selected has consequently been accurately eflected.

As is now apparent `from the foregoing, the FIGURE 2 addin" memory may be operated similarly to the counting memory of FEGURE -l to eiiect updating by decimal l ir" no end-around carry is employed and Or circuit 172 receives the count pulse.

For clarity, the normal read and write drive lines used to load information into and out of the FGURES l and 2 memories are not shown but may be added as required, using the above described input and output lines for these additional purposes as desired.

Thus it is apparent that this invention successfully achieves the various objects and advantages herein set forth.

Modifications of this invention not described herein fwill become apparent to those of ordinary skill in the art 7 after reading this disclosure. Therefore, it is intended that the matter contained in the foregoing description and the accompanying drawings be interpreted as illustrative and not limitative, the scope of the invention being deiined by the appended claims.

What is claimed is:

1. ln a memory which has at least one memory register including at least two successive bistable stages respec tively of lower and higher order each of which is switchable between first and second stable states and represents by its instant state a binary value of one digit of the binary number in the register, updating provisions comprising sensing means respectively coupled to said stages for developing a binary valued signal indicative of switching or no switching of the respective stage from its said iirst state to its second state, means applying a given signal to the said lower order stage for causing initial switching of that stage from its said first state to its second state if not already in the latter, means responsive to the said binary valued signal from the lower order sensing means for causing said given signal at that time to switch said lower order stage from its said second state to its rst state only if it was not initially switched as aforesaid from its rst to second state and to initially switch the said higher order stage from its said lirst state to its second state if not already in the latter, and means responsive to the said binary valued signal from the higher order sensing means for causing said ygiven signal at that time to switch the higher order stage from its said second state to its irst state only if it was not initially switched as aforesaid from its iirst to second state.

2. Apparatus as in claim 1 wherein each of the means responsive to the binary signal from the respective sensing means includes means for delaying the said given signal and Anding the delayed signal with an inverted output of the associated sensing means.

3. Apparatus as `fin claim 1 wherein each of the said means responsive to the binary signal from the respective sensing means comprises gating means including at least an inhibit gate having an inhibit input coupled to the output of the respective sensing means and a signal input and a delay passing said given signal when received at least to the respective signal input of the respective gating means, at the time correponding to the time the respective binary signal is being received at the respective inhibit input, the output signals of the lower order gating means being coupled to the input of the higher order delay and to the lower order stage to switch that stage from its said second to iirst state only if it was not initially switched from its lirst to second state as aforesaid, an output signal from the higher order inhibit gate being coupled to eiect switching of lthe higher order stage from its said second to irst state as aforesaid.

4. Apparatus as in claim 3 lwherein the output of the lower order inhibit gate is coupled to the input of the higher order delay and also to the input of the higher order stage to switch it as aforesaid and further to an input of the lower order stage `to switch that stage as aforesaid.

5. Apparatus as in claim 3 wherein each of said gating means includes :a second gate which is of the non-inhibit type and has two signal inputs respectively coupled to the output of the associated stage and the output of the associated delay, the output of the second gate for the lower order stage being coupled to the delay and input of the higher order stage with the output of the lower order inhibit gate being coupled to the lower order stage to switch that stage as aforesaid.

6. Apparatus as in claim 1 wherein each of said bistable stages includes a diiferent bistable magnetic element.

7. Apparatus as in claim 6 wherein each bistable magnetic element includes a ferromagnetic lilm which has uniaXial anistropy.

8. In a memory lwhich includes a plurality of memory registers each of which has at least two successive bistable 8. stages respectively of lower and higher order, said stages being switchable between said tirst and second stable states when primed with each stage representing by its instant state a binary value of one digit of Ithe binary number in the respective register, the improvement including updating provisions comprising a plurality of sensing means coupled one to each different order of stages for developing a binary valued signal indicative of switching or non-switching of any stage in the respective order from its said first `state to its second state, means for priming each. of the stages selectively by registers, means applying a given signal to the primed lower order stage of the selected register for causing initial switching of that stage from its said `first state to its second state if not already in the latter, means responsive to the said binary valued signal from the lower order sensing means for causing said given signal as it exists at that time to switch the said primed lower order stage from its said second state to its first state only if it was not already switched as aforesaid from its iirst to its second state and to initially switch the primed higher order stage of the selected register from its said rst state to its second state if not already in the latter, and means responsive to the said binary valued signal from the higher order sensing means for causing said given signal as it exists at that time to switch the said primed higher order stage from its said second state to its first state only if it was not initially switched as aforesaid from its first to second state.

9. Apparatus as in claim 8 wherein each'of the means responsive to the binary signal from the respective sensing means includes means for delaying the said given signal and Anding the delayed signal with an inverted output of the associated sensing means.

l0. Apparatus as in claim 8 wherein each of the said means responsive to the binary signal from the respective sensing means comprises gating means including at least an inhibit gate having an inhibit input coupled to the output of the respective sensing means and a signal input, and a delay passing said given signal when received atleast to the respective said signal input of the respect-ive gating means at the time corresponding to the time the respective binary signal is being received at the respective inhibit input, the output signals of the lower order gating means being coupled to the input of the higher order delay and to the lower order stages to switch the said primed lower order stage from its said second to first state only if it was not initially switched from its first to second state as aforesaid, an output signal from the higher order inhibit gate being coupled to effect switching of the said primed higher ordier stage from its said second to its first state as aforesai 11. Apparatus as in claim 10 wherein the output of the lower order inhibit gate is coupled to the input of the primed higher order stage to switch it as aforesaid and further to the input of the said primed lower order stage to switch that stage as aforesaid.

12. Apparatus as in claim 10 wherein each of said gating means includes a second gate which is of the noninhibit type and has two signal inputs respectively coupled to the output of the associated stage `order and the output of the associated delay, the output of the second gate for the lower stage order being coupled to the delay of the higher order stage and to an input of the primed higher order stage with the output of the lower order inhibit gate being coupled to the primed lower order stage to switch .that stage las aforesaid.

13. Apparatus as in `claim 8 wherein each stage of each of said registers 4includes a bistable magnetic element switchable between states by said given signal only if concurrently magnetically biased, said priming means including means for applying a biasing field to each magnetic element of any of said lregisters one register at a time.

14. Apparatus ias in `claim 13 wherein each of said magnetic elements is a ferromagnetic iilm having uniaXial anisotropy, and wherein the biasing `means is effec- 9 tive to apply a held transverse to the remanent magnetization axis of the lm in the plane therof.

15. A v'binary memory with updating provisions comprising a plurality of bistable stages switchable `between rst and second states, ya plurality of delays respectively associated with said staces, means for applying a signal to an input of lthe lowest order stage and concurrently to the delay associated therewith, md a plurality of means 'respectively responsive to die stage outputs tor conditionally applying the delayed signm associated with that stage to an input of .that `and of the `nent higher order stage and to the delay vfor that next stage.

16. A binary memory as in claim 15 wherein each of said stages includes a magnetic element switchable when biased lby the said signal respectively applied to the respective stage, and `further including means for magnetically biasing each of said magnetic elements.

i7. Apparatus as in claim l wherein each or the said conditionally applying means cludes an inhibit gate having an inhibit input coupled to the respective stage `output and a signal 'input coupled to the output of the respective delay, the output of the inhibit gate being coupled to the input of 4the delay for the next higher order stage, to said input of that stage, and to a second input of its own stage.

18. Apparatus `as in `claim wherein each of the said conI 'tionally applying means includes two gates only o-ne of which is of the inhibit type, the output of the associated delay being `crnipled to a signal input `of each or" those gates with the output ot" the associated stage being coupled to the inhibit input of the inhibit gate and to a second signal input of the other gate, the output of the inhibit gate being coupled as an input lto the `associated stage and the `output of the second gate being coupled as an input .to the next higher order stage and its delay.

19. Apparatus as in claim i8 usable as an adding memory and including an laddend register having a plurality of binary stages, -rneans for connecting a register stage output respectively to an input of each of said switchable bistable stages in parallel with the input of the delay associated with that stage, and means coupling the output of `the highest order non-inhibit type gate in parallel with the output or the lowest order register stage.

2Q. A binary memory with updating provisions cornprising a plurality of bistable stages ar anged in groups with each group re resentin g a binary number, each stage being switchable Ibetween rst and second states when primed, means for priming each of the stages selectively by groups, a plurality of delays respectively associated with corresponding ctage orders, means for applying a signal to an input of the lowest order stage and concurrently to the delay associated therewith for switching the primed lowest order stage if then switchable thereby, and a plurality of means respectively responsive to the difierent stage order outputs for conditionally applying the delayed signal associated 'with each stage order to an input of the primed stage in the same order, to the primed stage of the next higher order, and to the delay for that next stage.

21. Apparatus as in claim 2G wherein each of the said conditionally applying `means includes an inhibit input coupled to the output of the respective stage order and a signal input `coupled to the output of the respective delay, the output of the inhibit gate bein coupled to the input of the delay tor the next higher stage order, to the set-to first state input of each stage of that order, and to the set-to-second state input of each stage for its own order.

22. Apparatus as in claim wherein each of the said conditionally applying means includes two gates only one of which is of the inhibit type, the output of the associated delay ybeing coupled to a signal input of each of those gates with the output of the associated order of stages being vcoupled to the inhibit input of the inhibit gate and to a second signal input of the other gate, the output of CTI l@ the inhibit gate being coupled as a se-t-to-rst state input to each of the stages in the associated order and the output yof the second gate being coupled as a setto-second state input to each of the stages in the next higher order and to its delay.

23. A ybinary memory with updating provisions comprising `a plurality of bistable stages switchable between first and second states, a plurality of inhibit gates respectively coupled at an inhibit input to the stage outputs, a plurality of delays respectively coupled at their output to the inhibit gates at their signal input, means `for each stage for `applying an input signal 4to` the respective stage and delay including means coupling the delayed input signal of any stage as .the input signal to the next higher order stage and its associated delay, and means for coupling the output signal of each inhibit gate to an input of its respective stage.

24. A binary memory as in claim 23 wherein each of said bistable stages includes a magnetic element switchable when `biased by the input signal respectively applied to t1 e respective stage, and further including means for magnetically biasing each of the said magnetic elements.

25. A binary memory as in claim 23 usable as -a counting memory lfor updating by a decimal 1 count, wherein the output of each inhibit gate is the input signal for the respective stage delayed by the associated delay and is coupled both to the input of its own stage as well as to the input of the next higher order stage and its associated delay.

26. A. 'binary memory as in claim 23 usable as an adding memory, and further including an addend register having a plurali-ty of binary stages, and -means Afor coupling the said binary stage outputs respectively to an input of each of said bistable stages in parallel with the respectively associated delays, a plurality of non-inhibit type gates each having two inputs respectively coupled to the output of one of said bistable stages and to the output of the delay associated with that stage, the outputs of the 'non-inhibit gates being coupled in parallel respectively with the next higher order register stage outputs to the input and delay for that next higher order stage.

27. A binary memory with updating provisions comprising a plurality of bistable stages arranged in groups which represent respective binary numbers with each said stage being switchable between lrst and second states when primed, means `for selecting any one of said groups by priming each stage or" a group, a plurality of inhibit gates respectively coupled at an inhibit input to the stage order outputs, a plurality of delays respectively coupled at their output to the inhibit gates at their signal input, means for each order of stages for applying an input signal to the respective stage order and delay including means coupling the delayed input signal of any stage order as the input signal to the next higher order of stages and its delay, and means for coupling the output signal of each inhibit gate to an input 0f the primed stage in its respective order.

2S. A binary counting Amemory comprising a plurality of magnetic elements arranged in groups which represen-t respective lbinary numbers, each of said magnetic elements being switchable between rst and second stable states when biased, means `for selecting any one of said groups by magnetically biasing each element of a group, a plurality of inhibit `gates respectively coupled at an inhibit input to the diferent orders of elements with the output of each element in any one order being coupled to a respective gate inhibit input, a plurality of delays respectively coupled at their output to the inhibit gates at their signal input, means coupling the output of each inhibit gate in parallel to the input of the delay of the next higher order of elements if any, to an input of each element in any such next higher order, and to a second input of each element of the order of elements associated ith the respective inhibit gate, and means for applying a count pulse to the first input of the lowest order of elements and simultaneously to the input of the delay associated with that element order, the arrangement being such that upon applying said count pulse to the lowest order of elements, the group of elements which is then biased eiect propagation of that count pulse from the lowest order to the highest order depending upon the initial state of the biased element in each order, whereby the binary number originally in the biased group of elements is updated by a decimal 1.

29. A memory as in claim 28 wherein each of said magnetic elements includes a different ferromagnetic lrn having uniaxial anisotropy edecting a single easy axis of magnetization tand a single hard axis of magnetization transverse to said easy axis, and wherein the biasing means causes a iield along the hard axis of each lrn in any selected group thereof and the count pulse when applied to any film causes along the easy axis of that iilm a eld, which without the aid of the transverse biasing eld concurrently on that film, is insuticient to switch that film to its `opposite state even if of the proper polarity to do so.

30. A binary adding memory comprising a plurality of magnetic elements arranged in groups which represent respective binary numbers, each said element being switchable between iirst and second stable states when biased, means for selecting any one of said groups by biasing each element in a group, a plurality of pairs of gates one of which is `of the inhibit type and the other of which is of the non-inhibit type, each pair of gates being coupled to the output of a diierent numerical order of elements, a plurality of ldelays respectively coupled at their outputs to an input of each gate in each of said pairs, an addend register having a plurality of stages, a plurality of Or circuits respectively coupled to the outputs of said register stages, the output of each non-inhibit type gate being coupled to an input of the Or circuit for the nex-t higher order with the highest order non-inhibit gate output being coupled to an input of the Or circuit for the lowest order stage, the output of each inhibit `gate being coupled to an input of `each of the elements in its own order, and means coupling the output of the Or circuits respectively to the associated order `delays and also to an input of each element of the associated order thereof, the arrangement being such that the binary number of any group of biased elements is updated in accordance with the binary number supplied to said Or circuits `from said addend register.

31. A memory as in claim 3() wherein each of said magnetic elements includes a diierent ferromagnetic ilrn having uniaxial anisotropy eiecting a single easy axis of magnetization and a single hard axis of magnetization transverse to said easy axis, and wherein the biasing means causes a field along the hard axis of each i-lm in any selected group thereof and the count pulse when applied to any iilrn causes along the easy axis of that iilm a field, which without the aid of the transverse biasing field concurrently on that iilm, is insufficient to switch that film to its opposite state even if of the proper polarity to do so.

References Cited in the le of this patent UNITED STATES PATENTS 2,843,3 17 Steagall July 15, 1958 2,969,684 Auerbach Nov. 15, 1960 2,962,215 Haynes Nov. 29, 1960 2,968,797 Sard et al. Jan. 17, 1961 

8. IN A MEMORY WHICH INCLUDES A PLURALITY OF MEMORY REGISTERS EACH OF WHICH HAS AT LEAST TWO SUCCESSIVE BISTABLE STAGES RESPECTIVELY OF LOWER AND HIGHER ORDER, SAID STAGES BEING SWITCHABLE BETWEEN SAID FIRST AND SECOND STABLE STATES WHEN PRIMED WITH EACH STAGE REPRESENTING BY ITS INSTANT STATE A BINARY VALUE OF ONE DIGIT OF THE BINARY NUMBER IN THE RESPECTIVE REGISTER, THE IMPROVEMENT INCLUDING UPDATING PROVISIONS COMPRISING A PLURALITY OF SENSING MEANS COUPLED ONE TO EACH DIFFERENT ORDER OF STAGES FOR DEVELOPING A BINARY VALUED SIGNAL INDICATIVE OF SWITCHING OR NON-SWITCHING OF ANY STAGE IN THE RESPECTIVE ORDER FROM ITS SAID FIRST STATE TO ITS SECOND STATE, MEANS FOR PRIMING EACH OF THE STAGES SELECTIVELY BY REGISTERS, MEANS APPLYING A GIVEN SIGNAL TO THE PRIMED LOWER ORDER STAGE OF THE SELECTED REGISTER FOR CAUSING INITIAL SWITCHING OF THAT STAGE FROM ITS SAID FIRST STATE TO ITS SECOND STATE IF NOT ALREADY IN THE LATTER, MEANS RESPONSIVE TO THE SAID BINARY VALUED SIGNAL FROM THE LOWER ORDER SENSING MEANS FOR CAUSING SAID GIVEN SIGNAL AS IT EXISTS AT THAT TIME TO SWITCH THE SAID PRIMED LOWER ORDER STAGE FROM ITS SAID SECOND STATE TO ITS FIRST STATE ONLY IF IT WAS NOT ALREADY SWITCHED AS AFORESAID FROM ITS FIRST TO ITS SECOND STATE AND TO INITIALLY SWITCH THE PRIMED HIGHER ORDER STAGE OF THE SELECTED REGISTER FROM ITS SAID FIRST STATE TO ITS SECOND STATE IF NOT ALREADY IN THE LATTER, AND MEANS RESPONSIVE TO THE SAID BINARY VALUED SIGNAL FROM THE HIGHER ORDER SENSING MEANS FOR CAUSING SAID GIVEN SIGNAL AS IT EXISTS AT THAT TIME TO SWITCH THE SAID PRIMED HIGHER ORDER STAGE FROM ITS SAID SECOND STATE TO ITS FIRST STATE ONLY IF IT WAS NOT INITIALLY SWITCHED AS AFORESAID FROM ITS FIRST TO SECOND STATE. 